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1 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC features of MX10F201FC (80c51 with mtp memory and lcd) - 80c51 cpu core - 4.5 ~ 5.5v voltage range - 2 to 16mhz clock frequency - 16k bytes mtp memory for code memory - 512 bytes internal data ram - low power consumption - up to 16 digits lcd driver/controller - four 8 bit general purpose i/o ports - two standard 16-bit timers - on-chip watch dog timer - two channel pwm outputs - uart - 8 interrupt sources - 100 pin pqfp package - single clock or dual clock - emi compatibility features list - 80c51 cpu core - 4.5 ~ 5.5v operation voltage range - 2 to 16mhz clock frequency - 16k bytes mtp memory for code memory - more than 100 times program/erase cycles - more than 10 years data retention - 512 bytes internal data ram - low operation current - power saving modes - user friendly power control for active mode current - idle mode - sleep mode - power down mode, can be wake up by external interrupts or reset - lcd driver/controller - max. 16-digits display at 1/4 duty lcd - 1:1(static), 1:2, 1:3 or 1:4 selectable lcd multiplexing rate - 4 backplane driver, 32 segment driver - lcd directly drive capability with display memory - vlcd to control lcd driving voltage, (vlcd-vss) - 4x8 general purpose i/o ports - provide software i 2 c capability - two standard 16-bit timers (timer 0,1) - on-chip watch dog timer (wdt) - two channel pwm outputs - uart - up to 8 interrupt sources and 8 interrupt vectors - 4 external sources - 4 internal sources(timer0,timer1,watch timer and uart) - 100 pin pqfp package - single clock or dual clock - single clock mode : 2~16mhz system clock for cpu,timer0/1,wdt,uart and lcd - dual clock mode : 2~16mhz system clock for cpu,timer0/1,wdt,uart; while 32.768khz sub-system clock for lcd and watch timer. - system clock is either crystal or rc activated - emc(electro-magnetic compatibility) improved
2 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC pinning nc nc p26 p25 p24 p23 p22 p21 p20 nc nc nc p37/int3 p36/int2 p35/t1 p34/t0 p33/int1 p32/int0 p31/txd p30/rxd nc nc s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 s17 s18 s19 s20 s21 s22 nc s23 s24 s25 s26 s27 s28 s29 s30 s31 vlcd nc vss nc reset xtal1 xtal2 vdd nc vss rcp p00 p01 p02 p03 p04 p05 p06 p07 nc nc s4 s3 s2 s1 s0 bp3 bp2 bp1 bp0 nc vdd nc vss xtal3 xtal4 nc p17 p16 p15/pwm1 p14/pwm0 p13 p12 p11 p10 nc vpp nc nc p27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 MX10F201FC fig.1 pinning
3 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC table. 1 pin description i/o symbol pin \qfp 100 description o bp0-bp3 71~74 backplane drive output line 0 to 3. o s00-s31 75-79,83-100, segment drive output line 0 to 31. 2-10 i/o p00-p07 22-29 p ort:8-bit open drain bidirectional i/o port i/o p20-p27 42-48,51 port: 8-bit quasi-bidirectional i/o port with internal pull-up i/o p10-p17 56-63 quasi-bidirectional i/o lines p14 also for pwm channel 0 p15 also for pwm channel 1 i/o p30-p37 31-38 quasi-bidirectional i/o lines p30 31 also for uart receive p31 32 also for uart transmit p32-p33, also for external interrupt 0-3 p36-p37 p34 also for timer0 external input p35 also for timer1 external input i reset 15 reset input i vdd 18,69 p ositive power supply i vss 13,20,67 ground i xtal1 16 xtal connection input o xtal2 17 xtal connection output i xtal3 66 32.768khz, xtal input o xtal4 65 32.768khz, xtal output i rcp 21 rc oscillator resistor connection input i test/vpp 54 suppl y 12v power for programming / erasing i vlcd 11 lcd driver power supply note: 1. to avoid a 'latch-up' effect at power-on , the voltage on any pin (at any time )must not be higher than v dd +0.5 v or lower vss-0.5v respectively 2. the generation or use of a port 3 pin as an alternative function is carried out automatically by the associated special function register (sfr) bit is properly written .
4 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC fig.3 lcd driver block diagram fig.2 block diagram t0 t1 int0/1/2/3 33 xtal1 xtal2 reset t0/t1 two 16-bit counter cpu program memory 16kb data memory 512x8 ram pwm serial port 8-bit internal bus parallel i/o ports lcd unit t d r d s00-s31 bp3 bp2 bp1 bp0 8 8 8 8 watch dog timer p0 p1 p2 p3 alternative function of port3 3 3 3 vpp vdd vlcd vss pwm0 pwm1 3 3 3 3 lcd segment di splay regi ster lcd freq lcd duty bias enlcd divider timing/duty control, voltage selector lcd bias gen. backplane gen. segment gen. bp driver seg. driver lcd panel seg31 seg30?.seg0 bp0 bp1 bp2 bp3 lcon ext.clk lcd_clk 8 internal bus bp3_seg[31:0] bp0_seg[31:0] 4 bp_output [1:0] 32 seg_output [1:0] 32 4 vlcd vss
5 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC functional desctiption general the MX10F201FC is a stand-alone high-performance and low power microcontroller designed for use in many applications which need code programmability. the flash eprom offers customers to program the device themselves. this feature increases the flexibility in many applications, not only in development stage, but also in mass production stage. in addition to the 80c51 standard functions, the MX10F201FC provides a number of dedicated hardware functions. MX10F201FC is a control-oriented cpu with on-chip program and data memory. it can execute program with internal memory up to 16k bytes. MX10F201FC has four software selectable modes of reduced activity for power reduction : active power control, idle, sleep, and power-down. the idle mode freezes the cpu while allowing the ram, timers, serial ports, interrupt system and other peripherals to continue functioning. the power-down mode saves the ram contents but freezes the oscillator causing all other chip functions to be inoperative. power-down mode can be terminated by an external reset ,and in addition , by either of the four external interrupts. the sleep mode behaves like power down mode, but with lcd and oscillator still turning on. and sleep mode can be terminated as the power down mode does. instruction set execution the MX10F201FC uses the powerful instruction set of the 80c51. additional sfrs are incorporated to control the on-chip peripherals. the instruction set consists of 49 single-byte, 46 two-bytes, and 16 three-bytes instructions. when using a 16mhz oscillator, 64 instructions execute in 750 ns and 45 instructions execute in 1.5 us. multiply and divide instructions execute in 3 us. memory organization the central processing unit (cpu) manipulates operands in three memory spaces; these are the 256 bytes internal data memory (ram), 256 byte auxiliary data memory (aux-ram) and 16k byte internal mtp program memory (feprom). program memory the program memory address space of the MX10F201FC comprises an internal and an external memory space. the MX10F201FC has 16k byte of program memory on-chip. program protection if the user choose to set security lock in mtp memory, the program content is protected from reading out of chip. internal data memory the internal data memory is divided into three physically separated parts: 256 byte of ram, 256 bytes of aux- ram, and 128 bytes special function register area (sfr). these parts can be addressed as follows (see fig.4 and table. 2) - ram 0 to 127 can be addressed directly and indirectly as in the 80c51. address pointers are r0 and r1 of the selected register bank. - ram 128 to 255 can only be addressed indirectly . address pointers are r0 and r1 of the selected register bank. - aux-ram 0 to 255 is indirectly addressable as the external data memory locations 0 to 255 with the movx instructions. address pointers are r0 and r1 of the selected register bank and dptr. when executing from internal program memory, an access to aux_ram 0 to 255 will not affect the ports p0,p2,p3.6 and p3.7. sfrs can only be addressed directly in the address range from 128 to 255.
6 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC table. 2 internal data memory access location addressed ram 0 to 127 direct and indirect ram 128 to 255 indirect only aux-ram 0 to 255 indirect only with movx special function register (sfr) 128 to 255 direct only fig. 4 shows the internal memory address space. table 3 shows the special function register (sfr) memory map. location 0 to 31 at the lower ram area can be devided into four 8-bit register banks. only one of these banks may be enabled at a time. the next 16 bytes, locations 32 through 47, contain 128 directly addressable bit locations. the stack can be located anywhere in the internal 256 byte ram. the stack depth is only limited by the available internal ram space of 256 bytes. all registers except the program counter and the four 8-byte register banks reside in the sfr address space. - register - direct - register-indirect - immediate - base-register plus index-register-indirect. the first three methods can be used for addressing destination operands. most instructions have a 'destination / source' field that specifies the data type, addressing methods and operands involved. for operations other than movs, the destination operand is also a source operand. access to memory addresses is as follows: - register in one of the four 8-byte register banks through direct or register-indirect addressing. - 256 bytes of internal ram through direct or register-indirect addressing. bytes 0-127 of internal ram may be only be addressed indirectly as data ram. - sfr through direct addressing at address location 128-255. internal program memory 16 k 0 program memory indirect only --------------------- direct and indirect main ram 255 127 0 sfrs direct only sfrs auxiliary ram through movx access aux-ram overlapped space with different access schemes fig. 4 internal program and data mem ory address space internal data memory
7 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC symbol direct address(ex) r eset value p0 80h 1111,1111 sp 81 0000,0111 dpl 82 0000,0000 dph 83 0000,0000 pcon 87 0000,0000 tcon 88 0000,0000 tmod 89 0000,0000 tl0 8a 0000,0000 tl1 8b 0000,0000 th0 8c 0000,0000 th1 8d 0000,0000 p1 90 1111,1111 scon 98 0000,0000 sbuf 99 xxxx,xxxx p2 a0 1111,1111 ie a8 0000,0000 p3 b0 1111,1111 ip b8 x000,0000 lcon ba x001,1100 lcd0 bb 0000,0000 lcd1 bc 0000,0000 lcd2 bd 0000,0000 lcd3 be 0000,0000 lcd4 bf 0000,0000 intcon c0 0000,0000 lcd5 c1 0000,0000 lcd6 c2 0000,0000 lcd7 c3 0000,0000 lcd8 c4 0000,0000 lcd9 c5 0000,0000 lcda c6 0000,0000 lcdb c7 0000,0000 psw d0 0000,0000 lcdc d1 0000,0000 lcdd d2 0000,0000 lcde d3 0000,0000 lcdf d4 0000,0000 acc e0 0000,0000 wtl e3 0000,0000 wth e4 xx00,0000 ien1 e8 xxxx,xx00 ebtcon eb xxxx,001x b f0 0000,0000 pcon1 f1 x000,0100 ip1 f8 xxxx,xx00 pwm0 fc 0000,0000 pwm1 fd 0000,0000 pwmp fe 0000,0000 t3 (wdt) ff 1111,1111 table. 3 sfr registers map
8 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC i/o facilities MX10F201FC has one 8 bits port, port 0, which is open drain, and three 8 bits ports, port 1/2/3, which are quasi bi- directional ports. these four ports are fully compatible to standard 80c51's port 0/1/2/3. - port1: pins can be configured individually to provide 2 pwm outputs. - port3: pins can be configured individually to provide: external interrupt inputs (external interrupt 0/1/2/3); external inputs for timer/ counter 0 and timer /counter1, and uart receive / transmit. port pins which are not used for alternate functions may be used as normal bidirectional i/o pins. the generation or use of a port 1 or port 3 pin as an alternate function is carried out automatically by writing the associated sfr bit with proper value. fig. 5 i/o buffers in the MX10F201FC (ports 1,2,3) 2 oscillator penods strong pull-up p1 n p2 input buffer from port latch input data read port pin o p3 +5v i/o port 1,2,3
9 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC timer/counter MX10F201FC's timer/counter 0 and 1 are fully compatible to standard 80c51's. the MX10F201FC's contains two 16-bit timer/counters, timer 0 and timer 1. timer 0 and timer 1 may be programmed to carry out the following functions: - measure time intervals and pulse durations - count events - generate interrupt requests. timer 0 and timer 1 timers 0 and 1 each have a control bit in tmod sfr that selects the timer or counter function of the corresponding timer. in the timer function, the register is incremented every machine cycle. thus, one can think of it as counting machine cycles. since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. in the counter function, the register is incremented in response to a high-to-low transition at the corresponding samples, when the transition shows a high in one cycle and a low in the next cycle, the counter is incremented. thus, it takes two machine cycles (24 oscillator periods) to recognize a high-to-low transition. there are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle. timer 0 and timer 1 can be programmed independently to operate in one of four modes (refer to table 5) : - mode 0 : 8-bit timer/counter with devided-by-32 prescaler - mode 1 : 16-bit timer/counter - mode 2 : 8-bit timer/counter with automatic reload - mode 3 : timer 0 :one 8-bit timer/counter and one 8-bits timer. timer 1 :stopped. when timer 0 is in mode 3, timer 1 can be programmed to operate in modes 0, 1 or 2 but cannot set an interrupt request flag and generate an interrupt. however, the overflow from timer 1 can be used to pulse the serial port transmission-rgate generator. with a 16 mhz crystal, the counting frequency of these timer/counters is as follows: - in the timer function, the timer is incremented at a frequency of 1.33 mhz (oscillator frequency divided by 12). - in the counter function, the frequency handling range for external inputs is 0 hz to 0.66 mhz (oscillator frequency divided by 24). both internal and external inputs can be gated to the timer by a second external source for directly measuring pulse duration. the timers are started and stopped under software control. each one sets its interrupt request flag when it overflows from all logic 1's to all logic 0's (respectively, the automatic reload value), with the exception of mode 3 as previously described. tmod : timer/counter mode control register this register is located at address 89h. table. 4 tmod sfr (89h) 765 43210 gatec/ tm1 m0 gatec/ tm1 m0 (msb) (lsb) timer 1 timer 0 keep the above table with the following table
10 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC table. 5 description of tmod bits mnemonic po sition function timer 1 gate tmod.7 ti mer 1 gating control : when set, timer/counter '1' is enabled only while 'int1' pin is high and 'tr1' control bit is set. when cleared, timer/counter '1' is enabled whenever 'tr1' control bit is set. c/t tmod.6 timer or counter selector: cleared for timer operation (input from internal system clock). set for counter operation (input from 't1' input pin). m1 tmod.5 operation mode: see table 6. m0 tmod.4 operation mode: see table 6. timer 0 gate tmod.3 t imer 0 gating control: when set, timer/counter '0' is enabled only while 'int0' pin is high and 'tr0' control bit is set. when cleared, timer/counter '0' is enabled whenever 'tr0' control bit is set. c/t tmod.2 timer or counter selector: cleared for timer operation (input from internal system clock). set for counter operation (input from 't0' input pin). m1 tmod.1 operation mode: see table 6. m0 tmod.0 operation mode: see table 6. table. 6 tmod m1 and m0 operating modes m1 m0 function 0 0 8-bit timer/counter : 'thx' with 5-bit prescaler. 0 1 16-bit timer/counter : 'thx' and 'tlx' are cascaded, there is no prescaler. 1 0 8-bit autoload timer/counter : 'thx' holds a value which is to be reloaded into 'tlx' each time it overflows. 1 1 timer 0: tl0 is an 8-bit timer/counter controlled by the standard timer 0 control bits. th0 is an 8- bit timer controlled by timer 1 control bits. 1 1 timer 1 : timer/counter 1 stopped. tcon : timer/counter control register this register is located at address 88h. table. 7 tcon sfr (88h) 76543210 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 (msb) (lsb) keep the above table with the following table
11 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC table. 8 description of tcon bits mnemonic po sition function tf1 tcon.7 timer 1 overflow flag : set by hardware on timer/counter overflow. cleared when interrupt is processed. tr1 tcon.6 timer 0 overflow flag : set by hardware on timer/counter overflow. cleared when interrupt is processed. tf0 tcon.5 t imer 0 overflow flag: set by hardware on timer/counter overflow. cleared when interrupt is processed. tr0 tcon.4 timer 0 control bit : set/cleared by software to turn timer/counter on/off. ie1 tcon.3 interrupt 1 edge flag: set by hardware when external interrupt is detected. cleared when interrupt is processed. it1 tcon.2 interrupt 1 type control bit : set/cleared by software to specify falling edge/low level triggered external interrupt. ie0 tocn.1 interrupt 0 edge flag: set by hardware when external interrupt is detected. cleared when interrupt is processed. it0 tocn.0 int errupt 0 type control bit: set/cleared by software tospecify falling edge/low level triggered external interrupt.
12 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC interrupt system the MX10F201FC contains a 8-source 4 external interrupts, timer 0, timer1, watch timer and uart structures with two priority levels. each external interrupts int0, int1, int2, and int3 can be either level-activated or transition-activated depending on bits it0 and it1 in tcon sfr and it2, it3 in intcon sfr. the flags that actually generate these interrupts are bits ie0, ie1 in tcon and ie2,ie3 in intcon. when an external interrupt is generated, the corresponding request flag is cleared by the hardware when the service routine is vectored to, if the interrupt is transition- activated. if the interrupt is level-activated the external source has to hold the request active until the requested interrupt is actually generated. then it has to deactive the request before the interrupt service routine is completed, otherwise another interrupt will be generated. the timer 0 and timer 1 interrupts are generated by tf0 and tf1, which are set by a rollover in their respective timer/counter register (except for timer 0 in mode 3 of the serial interface). when a timer interrupt is generated, the flag that generated it is cleared by the on-chip hardware when the service routine is vectored to. ie : interrupt enable register this register is located at address a8h. table. 9 ie sfr (a8h) 76543210 ea ex3 ex2 es et1 ex1 et0 ex0 (msb) (lsb) keep the above table with the following table table. 10 description of ie bits mnemonic po sition function ea ie.7 disable all interrupt - low, all disabled. - high, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. ex3 ie.6 enable / disable external interrupt 3. - low, disabled - high, enabled ex2 ie.5 enable / disable external interrupt 2. - low, disabled - high, enabled es ie.4 enable / disable uart interrupt. - low, disabled - high, enabled et1 ie.3 enable / disable timer1 overflow interrupt. ex1 ie.2 enable / disable external interrupt 1. - low, disabled - high, enabled et0 ie.1 enable / disable timer0 overflow interrupt. ex0 ie.0 enable / disable external interrupt 0. - low, disabled - high, enabled
13 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC ip : interrupt priority register this register is located at address b8h. table. 12 ip sfr (b8h) 76543210 - px3 px2 ps pt1 px1 pt0 px0 (lsb) keep the above table with the following table table. 13 description of ip bits mnemonic po sition function - ip.7 reserved px3 ip.6 define external interrupt 3 interrupt priority level. - high, assign a high priority level. px2 ip.5 define external interrupt 2 interrupt priority level. - high, assign a high priority level. ps1 ip.4 define interrupt priority level of uart. pt1 ip.3 define timer1 overflow interrupt priority level. px1 ip.2 define external interrupt 1 interrupt priority level. - high, assign a high priority level. pt0 ip.1 define timer0 overflow interrupt priority level. px0 ip.0 define external interrupt 0 interrupt priority level. - high, assign a high priority level. ip1 : interrupt priority register 2 table. 14 ip1 sfr (f8h) 76543210 ------pwt0 pwt : define watch timer interrupt priority level. ien1 : interrupt enable register 2 table. 11 ien1 sfr (e8h) 76543210 ------ewt0 ewt : enable / disable watch timer interrupt.
14 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC table. 15 intcon sfr (c0h) 76543210 0 0 wtf wtr ie3 it3 ie2 it2 table. 16 description of intcon bits ie3/2 : external interrupt 3/2 edge flag. set by h/w when exteranl interrupt is detected, and cleared when interrupt is processed. it3/2 : external interrupt 3/2 type control bit. set/cleared by s/w to specify falling edge/low level triggered external interrupt. wtf : watch timer overflow interrupt flog. set by h/w when watch timer overflow occurred, and cleared by s/w or warm/cold reset. wtr : watch timer enable bit. set/ cleared by s/w table. 17 interrupt vectors & priority within levels source name prio rity within level vector address ext. interrupt0 ie0 1(highest) 0003h timer0 overflow tf0 2 000bh ext. interrupt1 ie1 3 0013h timer1 overflow tf1 4 001bh uart interrupt is 5 0023h ext. interrupt2 ie2 6 002bh ext. interrupt3 ie3 7 0033h watch timer overflow wtf 8 003bh
15 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC watch timer the watch timer module (see fig. 6) is clocked by 32.768khz external crystal, and generates interrupt request every 0.5 second. this value is derived from f timer = f osc / (256x64). the watch timer consists of an 8-bit timer register wtl and a 6-bit timer registers wth. the wtl register is triggered by the 32.768khz external crystal, and the wth register increases its value while wtl overflow occurs. when the overflow of wth occurs, the wtf bit in sfr intcon is set high automatically and an interrupt request is sent to the microcontroller. both of the timer registers wtl and wth can be loaded values by software. therefore the time interval of the watch timer interrupt request can be adjusted. this allows the watch timer to send interrupt request more frequently for some special application. the wtf can be set both by hardware and software, but it can only be cleared by software. the 32.768khz external oscillator is gated by the wtr bit in sfr intcon. if wtr is cleared, the watch timer registers will hold their values. in the idle and sleep states the watch timer remains active, and it wakes up the microcontroller while the watch timer overflow (i.e. wtf is set high) occurs. since this module is clocked by the 32.768khz external crystal, this module is disabled and consumes no power if there is no such crystal connected to the chip. fig. 6 watch timer internal bus write wtf, wtl, wth interrupt request wtr osc 32.768k wth (6-bit) load wtf (1-bit) load wtl (8-bit) load
16 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC lcd drivers the lcd module includes 4 by 32 pixel memory and can drive directly 4 backplanes and 32 segments outputs. thus, for common digit-typed lcd, MX10F201FC can have maximum 16 digits display. lcd control register (lcon) since MX10F201FC has several possible clocking alternatives : 2 to 16mhz system clock with possible second 32.768khz sub-system clock, programmers need to set up this register to get proper lcd frame scan rate. table. 18 lcon sfr (bah) 76543210 - lcdf2 lcdf1 lcdf0 md1 md0 bias enlcd . lcdf2,lcdf1,lcdf0: selection of lcd frame scan frequency table. 19 frame scan freq (hz) fclk divider (ext. clk) select 1/4 duty 1/3 duty 1/2 duty static - 000 : 16mhz fclk/2^18 61 81 61 61 - 001 : 12mhz fclk/(2^16*3) 61 81 61 61 - 010 : 8mhz fclk/2^17 61 81 61 61 - 011 : 4mhz fclk/2^16 61 81 61 61 - 100 : 2mhz fclk/2^15 61 81 61 61 - 101 : 1mhz fclk/2^14 61 81 61 61 - 110 :0.5mhz fclk/2^13 61 81 61 61 * - 111 : 32khz fclk/2^9 64 85 64 64 * note : dual clock mode is set by writing as "111". . md1,md0: mode bits, determine the lcd multiplex rate. table. 20 no of backpl anes pixel digits - 00 : static 1 (bp0) 32 4 - 01 : 1:2 2 (bp0,1) 64 8 - 10 : 1:3 3 (bp0,1,2) 96 12 - 11 : 1:4 4 (bp0,1,2,3) 128 16 . bias: set lcd voltage bias generator. - high, bias is 1/2(vlcd-vss) - low, bias is 1/3(vlcd-vss)
17 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC table. 21 lcd drive mode no of bps lcd bias voff(rms) v on(rms) contrast static 1 static 0 1 infinity 1:2 2 1/2 0.354 0.791 2.236 1:2 2 1/3 0.333 0.745 2.236 1:3 3 1/3 0.333 0.638 1.915 1:4 4 1/3 0.333 0.577 1.732 . enlcd: enable/disable lcd - low, all segment and backplanes drivers are set to the vss level. - high, the lcd is enable and digits display is possible. lcd segment display register : contain the on/off information of 4 by 32 segments of lcd table. 22 register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 lcd0 bbh seg1 seg0 lcd1 bch seg3 seg2 lcd2 bdh seg5 seg4 lcd3 beh seg7 seg6 lcd4 bfh seg9 seg8 lcd5 c1h seg11 seg10 lcd6 c2h seg13 seg12 lcd7 c3h seg15 seg14 lcd8 c4h seg17 seg16 lcd9 c5h seg19 seg18 lcda c6h seg21 seg20 lcdb c7h seg23 seg22 lcdc d1h seg25 seg24 lcdd d2h seg27 seg26 lcde d3h seg29 seg28 lcdf d4h seg31 seg30 bp3 bp2 bp1 bp0 bp3 bp2 bp1 bp0 lcd drive mode waveform : used to control the voltage level of backplane and segment outputs . static drive mode . 1:2 multiplex drive mode with 1/2 bias . 1:2 multiplex drive mode with 1/3 bias . 1:3 multiplex drive mode with 1/3 bias . 1:4 multiplex drive mode with 1/3 bias
18 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC fig. 7 static drive enlcd seg3 seg4 -- v lcd -- v lcd -- v ss -- v ss -- v lcd -- v ss -- v lcd -- v ss seg0 seg4 display data area address (note) *: don't care bbh bch bdh beh ***0 ***1 ***1 ***1 ***1 ***0 ***0 ***1 seg7 com0 -- v lcd - - -- -v lcd -- v lcd - 0 - -- -v lcd com0-seg0 (selected) com0-seg4 (non-selected) seg5 seg0 seg1 seg6 seg2 seg7 com0
19 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC fig. 8 1/2 duty (1/2 bias) drive enlcd -- v lcd -- v ss -- v lcd -- v ss -- v lcd -- v ss -- v lcd - - - 0 -- v ss -- v lcd -- v ss -- v lcd -- v ss -- v lcd -- v ss - - 0 -- v lcd -- v ss seg0 seg1 display data area address (note) *: don't care bbh bch **01 **01 **11 **10 seg3 seg2 com0 com1 com0-seg1 (selected) com0-seg2 (non-selected) seg3 seg0 seg2 seg1 com1 com0
20 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC fig. 9 1/2 duty (1/3 bias) drive enlcd -- v lcd -- v ss - - -- v lcd -- v ss - - -- v lcd -- v ss - - -- v lcd -- v ss - - -- v lcd -- v ss - - -- v lcd -- v ss - - - - - - 0 -- v lcd - v ss -- -(v lcd - v ss) - - - - 0 -- v lcd - v ss -- -(v lcd - v ss) seg0 seg1 display data area address bbh bch **01 **01 **11 **10 seg3 seg2 com0 com1 com0-seg1 (selected) com0-seg2 (non-selected) seg3 seg0 seg2 seg1 com1 com0
21 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC fig. 10 1/3 duty (1/2 bias) drive enlcd -- v lcd -- v ss -- v lcd -- v ss -- v lcd -- v ss -- v lcd -- v ss - -- v lcd -- v ss - -- v lcd -- v ss - - - 0 -- v lcd -- -v lcd - - 0 -- v lcd -- -v lcd seg0 seg1 display data area address (note) *: don't care bbh bch *111 *010 **** **01 seg2 com0 com1 com2 com0-seg1 (selected) com0-seg2 (non-selected) seg2 seg0 seg1 com2 com0 com1
22 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC fig. 11 1/3 duty (1/3 bias) drive enlcd -- v lcd -- v ss - - -- v lcd -- v ss - - -- v lcd -- v ss - - -- v lcd -- v ss - - -- v lcd -- v ss - - -- v lcd -- v ss - - - - 0 -- v lcd -- -v lcd - - 0 -- v lcd -- -v lcd seg0 seg1 display data area address (note) *: don't care bbh bch *111 *010 **** **01 seg2 com0 com1 com2 com0-seg1 (selected) com0-seg2 (non-selected) seg2 seg0 seg1 com2 com0 com1
23 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC fig .12 1/4 duty (1/3 bias) drive enlcd -- v lcd -- v ss - - -- v lcd -- v ss - - -- v lcd -- v ss - - -- v lcd -- v ss - - -- v lcd -- v ss - - -- v lcd -- v ss - - - - 0 -- v lcd -- -v lcd - - 0 -- v lcd -- -v lcd seg0 seg1 display data area address bbh 10110101 com1 com0 com2 com3 com0-seg0 (selected) com0-seg1 (non-selected) seg1 seg0 com3 com1 com0 com2
24 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC power saving modes : active power control, idle, sleep and power down modes in order to enable lowest power consumption in system application, MX10F201FC has user friendly power control mechanism as follows : 1) active power control : used to turn off un-used peripherals in specific applications. for instance, uart might not be used in audio cd application, then programmer can disable it to save power. 2) idle mode : used to turn off 80c51 during certain conditions. 3) sleep mode : used to turn off the whole system except lcd and possibly watch timer. 4) power down mode : turn off the whole system. pcon : power control register (pcon) pcon sfr (87h) 765 4 3 210 smod - sceer wle cf1 cf0 pd idc smod : doubl band rate bit for uart. sleep : sleep mode bit. setting it activates sleep mode, and could be terminated as the way to terminate the pull down mode. wle : watch dog load enable. this flag must be set prior to loading wdt and is cleaned when wdt is loaded. cf1/cf0 : general-prepose flag bit. pd : power - down bit. setting it activates power - down mode. idl : idle mode bit. setting it activates idle mode. active power control mode pcon1 : power control register 2 table. 23 pcon1 sfr (f1h) 765 4 3 210 - td uartd wdtd pwmd 1 wtd lcdd table. 24 description of pcon1 bits . td : timer0/1 disable bit. setting it to shut-down timer0/1. . uartd: uart disable bit. setting it to shut-down uart. . wdtd : watchdog timer disable bit. setting it to shut-down wdt. . pwmd : pulse width modulation disable bit. setting it to shut-down pwm. . wtd : watch timer disable bit, setting it to shu-down w t. . bit 2 must write "1" . lcdd : lcd disable bit. setting it to shut-down all lcd relative modules.
25 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC rc oscillator function MX10F201FC provides a rc oscillator function for the application that does not need very accurate system clock frequency and has to save the cost of crystal oscillator. as shown in fig. 13, to use the rc oscillator function as the system clock source, a suggested 50k~200k can be connected between the rcp pin and ground. the xtal1 pin has to be connected to ground or the internal clock system may be failed. when the system clock source comes from the crystal oscillator, the rcp pin is suggested to connect to vdd. the following table shows approximately the relationship between the rc oscillator clock frequency and the resistor value. resistor value (k ohm) rc oscillator clock frequency (mhz) 5v 3v 50 12~14 9~11 75 10~12 7.5~9 100 9~10 6.5~8 125 8~9 6~7.5 150 ~7.5 5.5~6.5 175 ~6.5 5.2~5.8 200 ~6 4.7~5.3 xtal1 xtal1 xtal2 xtal2 rcp rcp vdd resistor (a) (b) fig. 13 system clock connection way : (a) use rc oscillator as system clock source, (b) use crystal oscillator as system clock source. table. 25 rc oscillator reference table
26 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC clock system MX10F201FC has two possible clocking schemes with four combinations as follows : system clock sub-system clock single clock mode external 2 ~ 16mhz crystal (xtal1,xtal2) xtal3 is connected to gnd rc oscillator with external resister (rcp) xtal3 is connected to gnd and xtac1 is connected to gnd dual clock mode external 2 ~ 16mhz crystal (xtal1,xtal2) 32.768khzcrystal (xta l3,xtal4) rc oscillator with external resister (rcp) 32.768khz crystal (xtal3,xtal4) and xtac1 is connected to gnd the interaction between power saving modes and clock system is listed as follows : single clock dual clock 80c51 system clock system clock timer0/1, wdt, uart system clock system clock lcd system clock sub-system clock active mode all are active except watch timer all are active power control active mode individual peripheral is disabled by individual peripheral is disabled by corresponding active power control bit corresponding active power control bit idle mode 1) 80c51 is stopped 1) 80c51 is stopped 2) can be wake up by any interrupt 2) can be wake up by any interrupt sleep mode 1) all are st opped except lcd, system 1) all are stopped except watch timer, oscillator. lcd, sub-system oscillator. 2) can be wake up by external interrupts, 2) can be wake up by external interrupts,watch timer or reset power down mode 1)all are stopped 1) all are stopped 2) can be wake up by external interrupts 2) can be wake up by external or reset interrupts or reset
27 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC watchdog timer the watchdog timer (wdt) see fig.14 , consists of an 11-bit prescaler and an 8-bit timer formed by sfr t3. the timer is incremented every 1.5 ms, derived from the system clock frequency of 16 mhz by the following formula : f timer = f clk / (12 x (2048)). the 8-bit timer increments every 12 x 2048 cycles of the on-chip oscillator. when a timer overflow occurs, the microcontroller is reset. the internal reset signal is not inhibited when the external rst pin is kept 0 into high impedance, no matter if the xtal-clock is running or not. to prevent a system reset the timer must be reloaded in time by the application software. if the processor suffers a hardware / software malfunction, the software will fail to reload the timer. this failure will result in an overflow thus prevent the processor from running out of control. this time interval is determined by the 8-bit reload value that is written into register t3. watchdog time interval = [t3] x 12 x 2048 / oscillator frequency the watch-dog timer can only be reloaded if the condition flag wle (sfr pcon bit 4) has been previously set high by software. at the moment the counter is loaded wle is automatically cleared. in the idle state the watchdog timer and reset circuitry remain active. the watchdog timer is controlled by the watchdog enable signal ew (sfr ebtcon bit 1). a low level enables the watchdog timer. a high level disable the watchdog timer. fig. 14 watchdog timer t3 internal bus to reset circuitry timer t3 (8-bit) load loaden internal bus wle pd loaden prescaler (11-bit) clear clear f clk /12 write t3 ew pcon. 4 pcon. 1
28 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC pulse width modulated outputs the MX10F201FC contains two pulse width modulated output channels (see figure. 15). these channels generate pulses of programmable length and interval. the repetition frequency is defined by an 8-bit prescaler pwmp, which supplies the clock for the counter. the prescaler and counter are common to both pwm channels. the 8-bit counter counts modulo 255, i.e., from 0 to 254 inclusive. the value of the 8-bit counter is compared to the contents of two registers: pwm0 and pwm1. provided the contents of either of these registers is greater than the counter value, the corresponding pwm0 or pwm1 output is set low. if the contents of these registers are equal to, or less than the counter value, the output will be high. the pulse-width-ratio is therefore defined by the contents of the registers pwm0 and pwm1. the pulse-width-ratio is in the range of 0 to 1 and may be programmed in increments of 1/255. buffered pwm outputs may be used to drive dc motors. the rotation speed of the motor would be proportional to the contents of pwmn. the pwm outputs may also be configured as a dual dac. in this application, the pwm outputs must be integrated using conventional operational amplifier circuitry. if the resulting output voltages have to be accurate, external buffers with their own analog supply should be used to buffer the pwm outputs before they are integrated. the repetition frequency f pwm , at the pwmn outputs is give by : f pwm = f osc 2 x (1 + pwmp) x 255 this gives a repetition frequency range of 123hz to 31.4khz (f osc = 16mhz). at f osc = 24mhz, the frequency range is 184hz to 47.1khz. by loading the pwm registers with either 00h or ffh, the pwm channels will output a constant high or low level, respectively. since the 8-bit counter counts modulo 255, it can never actually reach the value of the pwm registers when they are loaded with ffh. when a compare register (pwm0 or pwm1) is loaded with a new value, the associated output is updated immediately. it does not have to wait until the end of the current counter period. both pwmn output pins are driven by push-pull drivers. these pins are not used for any other purpose. the pwm function is enabled by setting spr ebtcon bit 2,3. after reset, sfr ebtcon bit 2,3 need to be set to use p1.4 or p1.5 as the pwm output, otherwise p1.4& p1.5 are general i/o ports. prescaler frequency control register pwmp reset value = 00h pwmp (feh) 76543210 msb lsb pwmp.0-7 prescaler dividsion factor = pwmp +1. reading pwmp gives the current reload value. the actual count of the prescaler cannot be read. reset value = 00h pwm0 (fch) 76543210 pwm1 (fdh) msb lsb pwm0/1.0-7} low/high ratio of pwmn = (pwmn) 255 - ( pwmn) ebtcon sfr (ebh) 7654 3 2 1 0 ---- pwm1e pwm0e /ew - pwm1e : selection of p1.4 function as either pwm output or a port line, after reset pwm1e bit is low, and p1.4 is a normal port line. pwm0e : selection of p1.5 function as either pwm output or a port line, after reset pwm0e bit is low, and p1.5 is a normal port line. /ew : after reset, /ew bit is set, and wdt is disable.
29 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC internal bus pwm0 pwm0 pwm1 pwm1 pwmp 8-bit comparator output buffer 8-bit counter prescaler 1/2 t osc output buffer 8-bit comparator fig. 15 functional diagram of pulse width modulated outputs
30 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC uart this module is fully compatible to standard 80c51's uart.
31 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC mtp program memory features - 16 kilobyte electrically erasable internal mtp program momory. - programming and erasing voltage 12 volt - mtp (re) programming mechanism : - eprom like parallel programming protocol - parallel programming : - byte programming (8 us typical) - chip erase less than 0.5 second typical - 100 minimum erase/program cycles - advanced cmos flash memory technology - one security bit to protect internal rom code. general description MX10F201FC's mtp memory stores memory contents even after 100 erase and program cycles. the cell is designed to optimize the erase and programming mechanisms. in addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. the MX10F201FC uses 12 volt vpp supply to perform the program/erase algorithms. programming and program verify MX10F201FC is byte programmable by using 10us programming pulse and it requires separate program verify pulse to read out the data to check if program is ok or not. the typical programming time for each 1k bytes is about 10ms at room temperature.
32 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC programming specification parallel programming mode the parallel programming works in eprom-like programming protocol. the MX10F201FC mtp provides 100 times cycles endurance. and the MX10F201FC mtp needs a 11.5~12.5 volt vpp supply to perform the program/erase operation. specially note that lock 2 is used to security protection. so if lock 2 bit is programmed, then pgmvfy, ersvfy and normal read are disabled from parallel programming mode. lock 1 and lock 3 are not used in this chip. pin name symbol f unction p25~p20, p17~p10 p a13~pa8, pa7~pa0 a ddress input p07~ p00 q[7:0] data input/output p33 pceb chip enable input p27 poeb output enable input p32 pweb write enable input vpp vpp program supply voltage p26, p37, p31, p30 ms[3:0] flash mode selection vdd vdd power supply voltage (5v) vss gnd ground pin reset bp[3:0] vpp p33 p27 p32 p2[5:0] p1[7:0] p26, p37, p31, p30 vdd q[7:0] 4.5/5.5v vss 1 0000 11.5v ~ 12.5v pceb poeb pweb a[13:0] ms[3:0] xtal1 xtal2 p0[7:0] MX10F201FC table. 26 pin description
33 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC external ea p33 p27 p32 p 2[5:0] p26, p37, p 0[7:0] p0[7:0] pin p1[7:0] p31, p30 module i/o pvpp pceb poeb pweb pa[13:0] ms[3:0] puout[7:0] di or lock[3:1] pdout[7:0] dia standby 12v 1 x x x x ff,00 x normal read 12v 0 0 1 pa[13:0] 0000 data z initialize 12v 0 1 0.5sec x 1110 ff,00 x 000 pulse chip erase 12v 0 1 0.5sec x 0001 ff,00 x 000 pulse program 12v 0 1 10us pa [13:0] 0011 ff,00 d[7:0] pulses erase verify 12v 0 0 1 pa[13:0] 0100 data z program verify 12v 0 0 1 pa[13:0] 0101 data z pgm lock 12v 0 1 10us pa [1:0] 0110 ff,00 x lo ck[i] pulse 0 ->1 erase verify 12v 0 0 1 pa[1:0]=00 1001 lock[3:1] z lock pgm verify 12v 0 0 1 pa[1:0]=00 1011 lock[3:1] z lock read mft id 12v 0 0 1 pa[1:0]=00 1111 mftid(c2h) z read deviceid 12v 0 0 1 pa[1:0]=01 1111 d eviceid(0dh) z table. 27 parallel programming modes note : 1. program lock bits, program lock [1] to be 1 if pa [1:0] = 00 program lock bits, program lock [2] to be 1 if pa [1:0] = 01 program lock bits, program lock [3] to be 1 if pa [1:0] = 1x 2. verify erased lock bits if pa [1:0] = 00 3. verify programmed lock bits if pa [1:0] = 00 4. read manufacture id, device id pa [1:0] = 00 : manufacture id (c2h) pa [1:0] = 01 : device id (0dh)
34 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC program and program verify flowchart start first address vdd= 5v vpp = 12v x=0 program one 10us pulse pass device fail device program verify last address normal read all x=20 fail x=x+1 yes no yes increment address no yes fail pass
35 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC erase and verify flowchart st art x = 0 vdd= 5v vpp = 12v program array all zero (0 ~ 16kb) & lock chip erase (0.5s) erase verify lock erase verify array (16kb) pas s device x = 30 fail device fail => x=x+1 pass yes no
36 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC program lock and program verify lock flowchart start lock address pa [1:0] vdd= 5v vpp = 12v x=0 program lock 10us pulse pass device fail device program verify lock x=20 fail x=x+1 yes no pass
37 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC a. timing diagram of read signature and normal read operations taa tce toe tdf tmsce min. 0 100 max. 130 130 50 20 unit ns ns ns ns ns a 0=0 / a 0=1 taa tce tdf out mfg id / device id vpp web address ceb oeb ms[3:1] data toe tmsce tmsce
38 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC b. timing diagram of erase and erase verify array operation tvps tms tces ter tew tev tmsce min. 2 200 100 100 0.5 100 max. 200 unit us ns ns ns s ns ns
39 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC tvps tms tces ter tew tev tmsce min. 2 200 100 100 0.5 100 max. 200 unit us ns ns ns s ns ns c. timing diagram of erase and erase verify lock operation
40 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC d. timing diagram of program and program verify operation tas tds tdh tvps tces tms tpr tpw tpv tmsce min. 100 100 100 2 100 200 100 8 100 max. 200 unit ns ns ns us ns ns ns us ns ns
41 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC e. timing diagram of program lock and program verify lock operation tas tds tdh tvps tces tms tpr tpw tpv tmsce min. 100 100 100 2 100 200 100 8 100 max. 200 unit ns ns ns us ns ns ns us ns ns note : out = { xxxx, lock [3], lock [2], lock [1], x} 0110 1011 pa [1:0] pa [1:0] =00
42 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC limiting value symbol p arameter min max unit vdd supply voltage 4.5 5.5 v vi input voltage (all inputs) -0.5 vdd + 0.5 v v vpp voltage on vpp pin to vss 0 13 v i ol(max) maximum iol per i/o pin 15 ma tstg storage temperature -65 150 o c tamb operating ambient temperature(for all devices) 0 70 o c dc eleectrical characteristics symbol p arameter conditions min. typ. max. unit supply vdd normal operation supply voltage 4.5 5.5 v i dd operation supply current f osc =16mhz 10 20 ma f osc =12mhz 8 ma f osc =4mhz 4 ma i id supply current in idle mode f osc =16mhz 8 12 ma f osc =12mhz 6 f osc =4mhz 2 i slp supply current in single sleep mode f osc =16mhz 4 8 ma f osc =12mhz 3 f osc =4mhz 1 i dslp supply current in dual sleep mode f osc =16mhz 50 100 ua f osc =12mhz 45 f osc =4mhz 25 i pd supply current in power-sown mode f osc =16mhz 1 30 ua f osc =12mhz 1 f osc =4mhz 1 inputs r inp input resistance reset vdd=4.5v to 5.5v 15 100 kohm i l input leakage current; reset vdd=5v 120 ua v ih1 input high voltage to 0. 7vdd vdd+0.5 v xtal1, xtal3, reset ports p0~p3 v il input low voltage -0.5 0.2vdd-0.1 v v ih input high voltage, except 0. 2vdd vdd+0.5 v xtal1, xtal3, rst +0.9 i il logical 0 input current vi n=0.4v, vdd=5v -1 -100 ua i tl logical 1 to 0 transi tion current vin=2.0v -650 ua
43 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC outputs : p0~p3 symbol p arameter conditions min. typ. max. unit v ol output low voltage vdd=4.5v, i ol =1.6ma 0.4 v v oh output high voltage vdd=4.5v, i oh =- 3.3ma vdd-0.7 v i ol low level output sink current v o <0.4v, vdd=5v 10 13 ma i oh high level pull-up output source current strong pull-up v o =vdd-0.4v, vdd=5v 4 6 ma weak pull-up v o =vdd-0.4v, vdd=5v 15 30 ua c io pin capacitance (except ea) 15 pf symbol p arameter conditions min. typ. max. unit supply vlcd lcd operation supply voltage 4.5 vdd v vss dc voltage component; all backplane 100 mv and segment drivers lcd driver outputs r bp output impedance bp0~bp3 6 20 kohm r s output impedance s0~s31 6 20 kohm f lcd lcd scan frequency ratio: 1:1, 1:2, 1:4 61 hz ratio: 1:3 81 hz lcd driver characteristics
44 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC 5.5 5 4.5 3.3 3 2.7 100kohm 9.36 9.19 8.7 7.4 6.48 6.15 40kohm 15. 98 14.81 14.29 10.95 10.12 8.99 20 15 10 5 0 5.5 5 4.5 3.3 3 2.7 100kohm 40kohm mhz v fosc - vdd rcp oscillator characteristics ac characteristics symbol p arameter conditions min. typ. max. unit system (cpu) clock fc oscillator frequency 2 16 mhz 32.768khz lcd oscillator f xtal 32.768khz oscillator frequency 32.768 khz
45 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC package information 100-pin pqfp a b e cd i h g f 13 0 31 50 51 80 81 100 n m j k l p o item millimeters inches a 24.80 .40 .976 .016 b 20.00 .13 .787 .005 c 14.00 .13 .551 .005 d 18.80 .40 .740 .016 e 12.35 [ref] .486 [ref] f .83 [ref] .033 [ref] g .58 [ref] .023 [ref] h .30 [typ.] .012 [typ.] i .65 [typ.] .026 [typ.] j 2.40 [typ.] .094 [typ.] k 1.20 [typ.] .047 [typ.] l .15 [typ.] .006 [typ.] m .10 max. .004 max. n 2.75 .15 .108 .006 o .10 min. .004 min. p 3.30 max. .130 max. note: each lead centerline is located within .25mm[.01 inch] of its true position [tp] at a maximum material condition.
46 p/n:pm0730 rev. 0.1, feb. 14, 2003 MX10F201FC revision description page date 0.1 modify table. 15 intcon sfr (c8h) --> (c0h) p14 sep/06/2002
m acronix i nternational c o., l td. headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office: tel:+32-2-456-8020 fax:+32-2-456-8021 japan office: tel:+81-44-246-9100 fax:+81-44-246-9105 singapore office: tel:+65-348-8385 fax:+65-348-8096 taipei office: tel:+886-2-2509-3300 fax:+886-2-2509-2200 m acronix a merica, i nc. tel:+1-408-453-8088 fax:+1-408-453-8488 chicago office: tel:+1-847-963-1900 fax:+1-847-963-1909 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice. mx10fm201fc

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